1. Field of the Invention
The present invention relates to electron beam lithography. More particularly, the present invention relates to an electron beam mask and to a method of manufacturing a semiconductor device using the same.
2. Description of the Related Art
The manufacturing of a semiconductor device requires the controlled implanting of impurities into a small area on a semiconductor substrate. A lithographic process is used for defining this small area. That is, a resist is formed over the entire surface of a wafer. Ultraviolet rays, an electron beam or X-rays are passed through a mask to selectively expose the resist. Subsequently, the exposed resist is developed and patterned, whereby a semiconductor device pattern is formed on the semiconductor substrate.
The photo mask for selectively exposing a resist to ultraviolet rays transfers an image to the entire surface of the wafer in a one-time exposure process. That is, patterns corresponding to a plurality of chips are defined by the photo mask and images of the photo mask patterns are transferred all at once to the wafer, whereby the process is characterized by a high manufacturing yield. However, the resolution and registration are limited to 1 xcexcm and xc2x13 xcexcm, respectively, due to the diffraction of light passing through the mask.
Meanwhile, lithographic processes must offer higher resolution and registration to meet the demand for more highly integrated semiconductor devices. For this reason, an electron beam (E-beam) lithographic method using a focused E-beam has emerged as the prevailing method of forming dense circuit device patterns. Although electrons have a wave property, the wavelength of an E-beam is extremely short. Thus, a lithographic method using an E-beam is better suited to forming highly-integrated semiconductor circuits than a photo lithographic method using ultraviolet rays.
FIG. 1 is a cross-sectional view of a mask of an E-beam lithographic system. In particular, the mask is used in SCAttering with Angular Limitation in Projection Electron-beam Lithography (SCALPEL) and will thus be referred to hereinafter as a SCALPEL mask. In the SCALPEL mask, a silicon nitride layer and a resist layer are formed on the back surface of a wafer. A membrane 12 made of a silicon nitride layer of about 60 nm is formed on the front surface of the wafer. The silicon nitride layer at the back surface of the wafer is patterned using the resist layer. Supporting bars 10 are formed by etching the back surface of the wafer using the patterned silicon nitride layer. In the meantime, mask patterns 14 made of tungsten or chrome 10 are formed on the membrane 12. If the mask is formed with defects, e.g., if tungsten or chrome patterns are formed where they should not be formed, then such tungsten or chrome patterns are removed using a laser beam. At this time, the laser beam may damage the membrane 12. On the other hand, if tungsten or chrome patterns are not formed where they should, then a deposition process is performed to form the missing tungsten or chrome patterns. This deposition process requires time, and leaves additional defects in the previously formed mask pattern.
Furthermore, current E-beam lithography is performed using an E-beam of 1 mm by 1 mm. Therefore, the images defined by the patterns of the mask can not all be transferred to the surface of the wafer in only one E-beam exposure process.
That is, the E-beam exposure process must be repeated several times for each wafer. Thus, the E-beam lithography is slower than lithography processes using light. In other words, E-beam lithography using an E-beam mask has been characterized as providing a considerably low yield.
Accordingly, an object of the present invention is to provide an E-beam mask by which E-beam lithography can be carried out to produce semiconductor devices at a considerably higher yield than has heretofore been possible.
Likewise, an object of the present invention is to provide a lithographic method for manufacturing a semiconductor device using an E-beam and which method provides a considerably higher yield than conventional E-beam lithographic processes.
To achieve the above-mentioned first object, the present invention provides an electron beam (E-beam) mask comprising: a membrane, a main pattern including a plurality of stripes formed on the membrane, and a respective non-defective dummy stripe formed in spare room on the membrane in correspondence with each defective stripe in the main pattern. The dummy stripe(s) may be part of at least one dummy pattern each of which includes the same number of dummy stripes as the number of stripes in the main pattern. Alternatively, only dummy stripes corresponding to the defective stripes of the main pattern may be formed on the membrane. Still further, the dummy stripe(s) may be part of a pattern discrete from the main and dummy patterns when the stripe(s) of the dummy pattern(s) corresponding to the defective stripe(s) of the main pattern also has/have a defect.
The E-beam mask may be a SCALPEL mask having stripes that are 1 mm by 12 mm or a Projection Exposure with Variable Axis Immersion Lense (PREVAIL) mask having stripes that are 1 mm by 1 mm. The main and dummy patterns are made of a plurality of chrome or tungsten patterns that are only semi-transparent to the E-beam, and the membrane is made of silicon nitride.
To achieve the second object, the present invention provides lithographic methods of forming a semiconductor device, in which a non-defective dummy stripe is used for each E-beam exposure process instead of a defective stripe of the main pattern.
In a first one of such methods, an E-beam mask is manufactured to include a main pattern comprising a plurality of stripes disposed on a membrane, and a dummy pattern comprising dummy stripes formed in spare room on the membrane outside the region bounded by the main pattern. All of the stripes of the E-beam mask are inspected for defects and information on the defective stripes is stored. The stripes in the E-beam mask are then used in the exposure of a resist. In particular, based on the stored information, the E-beam exposure processes are carried out using the non-defective stripes of the main pattern, and the non-defective stripe(s) of the dummy pattern that correspond to the defective stripe(s) of the main pattern.
However, if the dummy stripe(s) of the dummy pattern(s) corresponding to a defective stripe of the main pattern is/are also found to be defective, an additional dummy stripe is formed in any spare room on the membrane outside the regions bounded by the main and dummy patterns. When the lithographic process reaches the defective stripe of the main pattern, the additional dummy stripe is used for the next E-beam exposure process instead of the defective stripe of the main pattern and the corresponding defective stripe(s) of the dummy pattern(s).
In another method, the main pattern of stripes is formed on the membrane, the stripes of the main pattern are inspected for defects, and then dummy stripes each corresponding to a defective one of the main stripes are formed in spare room on the membrane outside the region bounded by the main pattern. The E-beam exposure processes are carried out in a sequence using the non-defective stripes of the main pattern, and each non-defective dummy stripe corresponding to a respective defective stripe of the main pattern.
The present invention can also be applied to the manufacturing of semiconductor devices wherein the same circuit pattern is to be repeated in several places across the semiconductor substrate, e.g. in DRAM cells.
In particular, a main pattern including a plurality of stripes is formed on a membrane. Some of the stripes have the same internal pattern as is consistent with the nature of manufacturing DRAM cells. The stripes are inspected for defects and information indicative of which of the stripes have the same patterns and which of the stripes have defects is stored. A determination is made as to whether all of the stripes having the same pattern are defective. If so, a dummy stripe corresponding to the defective stripes having the same pattern is formed on the membrane in spare room outside the region bounded by the main pattern.
E-beam exposure processes are then performed based on the stored information. More specifically, the E-beam exposure processes are carried out in a sequence wherein the E-beam is directed through the non-defective stripes of the main pattern. When a defective stripe in the main pattern is reached during the course of said sequence, the E-beam is directed instead through one of the stripes of the main pattern that has the same pattern as the defective stripe as long as that stripe is also non-defective. However, if all of the stripes having the same patterns are defective, the E-beam is instead directed through the corresponding dummy stripe.
In the methods described above, after the E-beam exposure process of is completed, the resist layer is developed, and a semiconductor device pattern is formed on the semiconductor substrate using the developed resist layer.